An Optimized Two Stages Low Power Sinc Filter for !" Modulators
نویسندگان
چکیده
This paper presents the design of a low power sinc3 filter implementing a decimation factor by 16 and suitable for a second order !" modulators running at 256 MHz. The circuit uses the cascade of two stages and consumes only 48.1 μW, with 1.2 V voltage supply. The ultra-low power features come from both an architectural optimization and the use of suitable transistor level schemes. The circuit, simulated in a 0.18-μm CMOS technology, improves the overall power consumption by about 75.4% with respect to an already optimum conventional design.
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